Theories of Moral Standing

Question: Discuss the moral standing of each of the individual as in Jessica, Marco, Aunt Maria and Dr. Wilson? Answer: The case suggests the moral standing of each of the individual as in Jessica, Marco, Aunt Maria and Dr. Wilson. The moral stand point of each can be judged from a Theoretical perspective: Jessica: The pregnant woman who had the fetus inside her and when she hears about the news of abnormality the rationality of having a deformed baby kicks in. The theory of Kants Categorical Imperative is use here (Jaworska Tannenbaum, 2013). The rationality in use is the sake of the baby who on birth is not assured to have a normal life so this is acting as the morale agent too for her in choosing the right state for her child and her future with Marcos. Marco: The husband and the father to the child is guided by the Benthams Principles of Greatest Happiness Principles which makes him reject the rationality and focus upon the condition of Jessica where he feels the news would affect there well being. He takes time to seek for a more suitable moment to disclose the news which for him is to give his wife more time to think and recover. Again, Wetlesens theory of moral standing is also observed when the husband actually decides to follows the wifes will of choice and independence of making her own decisions about aborting or keeping the baby. This gives the standing of Marcos as a standing of lowest possible negative impact on both the future and well being of there family by letting the wife consider the best option (Hancock, 2013). Aunt Maria: The lady shows the cause of Religion to suggest the family to keep the baby. This behavior has a Parentelism effect playing inside her which makes her interfere with the well being of others irrespective of their own personal choices. The theory suggests that the parentalism claims that the interference would do well for other, upon whose judgment the interference is being made, and it would be a better off decision. In the case, Aunt Marias case is that of interference into the well being of the couple making points of spirituality over rationality (Dworkin, 2002). Dr. Wilson: The stand point of Dr. Wilson in the case is best elaborated by the Kants theory which suggests that the actions are morally right in virtue of their motives. Thus the duty of the Doctor is having inclination over the consequence and interest of others. The relevance of the information is to the mother in the case, from the doctors perspectives (Loyno.edu, 2014). Thus the doctor kept his duty over the husbands intentions or the Aunts spiritual concerns. For the researcher the perspective of the Doctor is the most rational standing as the need to communicate the necessary information to the patient was chosen over other obligations. This is to give the patient all needed information and keep them aware so that the individual patient can take the decision. The pregnancy and the well being of the child is the concern for Jessica over the Aunt or Marcos, therefore the most rational approach in the case can be ascribed to the Doctors moral stand point. References Dworkin, G. (2002). Paternalism. Plato.stanford.edu. Retrieved 27 May 2015, from https://plato.stanford.edu/entries/paternalism/ Hancock, S. (2013). Theories of Moral Standing. Academia.edu. Retrieved 27 May 2015, from https://www.academia.edu/393647/Theories_of_Moral_Standing Jaworska, A., Tannenbaum, J. (2013). The Grounds of Moral Status. Plato.stanford.edu. Retrieved 27 May 2015, from https://plato.stanford.edu/entries/grounds-moral-status/ Loyno.edu,. (2014). Kant's Theory. Retrieved 27 May 2015, from https://www.loyno.edu/~folse/Kant.html#2

How to Write Your Own Essay For Free

How to Write Your Own Essay For FreeFree sample essays can help you get an idea of what it would take to write your own essay. I have written several free sample essays and some of them were written from a professional perspective, but others were written from a beginner's perspective.Some of the websites that offer sample essays are on an old school model where they have past assignments and lessons. There is not much of a difference when it comes to writing a lesson plan or a prompt. You simply go online, type in your name, and fill out a form.Another benefit of using a free sample essay is that you are able to write and revise the sample for many times before you submit it. This is a big time saver. I did this with several of my essays.Finally, you do not need to be an expert writer in order to write a sample essay for yourself. You will find many people who are experts in their field and are willing to help you improve your writing.Some websites are known for providing excellent guidance on how to create an essay that is both engaging and interesting. They will provide you with a writing sample or two that are very easy to read. It may seem like they are copying each other's work, but they are actually giving you a good start.Writing sample essays can be a good practice tool for you. The goal is to have a piece of material that you can use as you continue to develop your own style and voice. Most websites offer free samples that you can read and implement into your own style.I would recommend that you have your own voice as you learn more about writing. In order to do this, I encourage you to follow the guidelines that are offered by these sites. Even if you don't have any writing experience, you can still follow the suggestions that are offered.

The Application of Global Strategic Management model to Problems that Starbucks faces in Australia

Executive Summary This report will put in place an operational strategy for the turnaround of the Starbucks Australia segment after a widespread closure of stores. The report analyses the competitive environment of the company and come up with the possible solutions to the problems of Starbucks Australia.Advertising We will write a custom research paper sample on The Application of Global Strategic Management model to Problems that Starbucks faces in Australia specifically for you for only $16.05 $11/page Learn More The report will also address the long term survival strategy for the Starbucks Australia so as to meet it meet its global market leadership and great customer experience targets. All the proposed solutions in this report will be in line with overall global management strategy for Starbucks Corporation. Global Coffee Industry The global coffee industry has been experiencing crisis of low coffee prices and generally low profitability in the who le value chain. This has led to coffee farmers mostly small scale entrepreneurs in central and South America to incur losses yet they are supposed to be breaking-even. The evident lesser process of coffee were as a result of high supply of coffee in the market. With this excess supply, quality of the green coffee went down. This not only posed problems to the producers but also industry players including Starbucks Corporation which is a global leader. With cheap and low quality coffee in the market, competitors of Starbucks capitalized on this so that in the long run there were low sales on Starbucks stores. Several challenges also accompanied this internal coffee crisis; consumers felt that they had less significant benefits in the whole coffee value chain. This structural problem needed the whole industry players to put together an industry strategy to check on the glut and increased quantity of defective coffee in the market. Starbucks Growth strategies Starbucks being the worlds ’ premier roaster and retailer of coffee has had a long term strategy of being the global leader in the coffee industry. The company’s’ growth strategy has enabled the company to spread to over 50 countries as indicated in their 2009 financial report. The company has achieved this position as a global leader and respected coffee brands through their good business plan of the store level efficiency, being innovative in their products, strategic channels of distribution, great customer experience in the retail stores and building of strategic linkages through licensing of different stores and joint ventures.Advertising Looking for research paper on business economics? Let's see if we can help you! Get your first paper with 15% OFF Learn More Starbucks corporation actually appreciated the strategic management strategies for increasing the shareholders value though, like any other multinational it has experienced different challenges in several locati ons which in the past has even worsen to an extend of downsizing by closure of several stores both in the US and international markets including Australia. Downsizing in a corporation is a strategic move usually designed to add value to the shareholders in the long run but mostly viewed by the customers and the other industry players as failure of an institution. With the aggressive global expansion strategy and the concept of market blanketing, Starbucks was bound to meet different challenges as much as it gained in other geographical locations. Challenges facing Starbucks globally Global expansion on its owned posed challenges relating to the political and legal factors, economic trends in different states, competition from local firms, consumer preferences, technological challenges and social-cultural issues. Starbucks like any other commercial corporation also do have an overriding goal of adding stockholders value through remaining profitable. This brings the strategic decision making accuracy into focus. All strategic decisions are arrived at after a rigorous process of evaluation of internal and external environment with all strengths and weaknesses having been taken into consideration. The company strategy is mainly to take advantage of its strengths and be cautious on its weaknesses hence it usually draws a road map unto the company’s future position. Starbuck in their strategic endeavor of being a global leader in the roasted coffee market has faced lots of challenges especially in being compliant to different political and legal environments. This is a challenge which has been achieved through their concept of strategic alliances through joint ventures and licensing of various global distributors. The Starbucks concept of serving high quality coffee products has given the company the image of serving the economically stable members of the society. This means that with high quality at stake, the company will lock themselves out of mass market where all products are served. The economic abilities of different countries has made Starbucks to be limited by the economic situations in different locations since some in some countries like in developing nations spending $5 on a cup of coffee is impossible. This has limited their growth strategy.Advertising We will write a custom research paper sample on The Application of Global Strategic Management model to Problems that Starbucks faces in Australia specifically for you for only $16.05 $11/page Learn More Different social-cultural background globally has been a challenge Starbucks has been facing. Different cultures have their favorite foods and drinks this puts Starbucks coffee including their concept of great store experience face a challenge of irrelevance and resistance. Starbucks challenges in Australia Starbucks Australia is one of the leading global segments. The Australian Starbucks has experience lots of challenges which lead to a closure of several retails stores. An analysis of the cause of the closures revealed several challenges regarding the locations of the different stores, unprofitability and low demand among other reasons. The following are some of the critical challenges facing Starbucks Australia; Poor marketing The Starbucks Australia did not do a lot of commercials and expected to ride on their fame on the US markets consequently leaving this critical business responsibility. Selling the high quality aspect of their coffee could have been very easy but forgoing such important strategic responsibility was a failure on the segments management. Without aggressive marketing apart from the branding aspect, Starbucks just left the market to their competitors including Gloria coffee, Melbourne and Espresso. Also poor location of Starbucks stores contributed to their poor marking strategy. Most stores were located in non strategic areas with low number of potential customers. This is another factor which greatl y contributed to the unprofitability of this stores hence had to be closed. Employee Motivation Starbucks Corporation worldwide had been known to be one of the good employers but the Australian segment has issues with poor staff remunerations consequently experiencing a less motivated workforce. Maintaining a highly skilled human resource gives a competitive edge to an institution. With a scenario of having expatriates’ performing an initial local operational market penetration strategy without prior market experience in Australia while the local management is later employed with low pay, the company is bound to face lots staff turnover. Pricing policy The Starbucks pricing policy should have been restructured to suite Australian market. The Starbucks prices of the different coffee products were perceived too high and products were only purchased for leisure treat and not as a necessity drink. The pricing concept should have been made even very local backed up by an aggressiv e marketing.Advertising Looking for research paper on business economics? Let's see if we can help you! Get your first paper with 15% OFF Learn More Coffee products The Starbucks products were perceived as international and this gave the local market an illusion that the products were not theirs hence unnecessary. Starbucks though with a very nice corporate social responsibility did not build attachment with the local community. Rapid expansion With expansion as their corporate strategy Starbuck Australia should have had a localized approach which would have allowed for a market testing. It was not necessary for more than fifty stores to be closed yet the local management should have known that a particular number of stores could have been optimum for the Australian market. Uncontrolled expansion always can cause erosion of the shareholders funds which makes the overall objective of expansion a futile exercise. Recommended strategy for Australia The Starbucks Australia’s challenges are all strategic management problems with little business policy problems. Strategic managements entails decisions which are unstructured and affecting the going concern aspects of the business entity (Choo, 2002). It is the role of the top management to make decision after assessing their internal environment and also the external environment which is usually to some extent very unpredictable. According to Harley (2004) strategic management decisions for global corporations will always aim at maximizing the profitability consequently the shareholders value. These decisions will always include expansions and where necessary downsizing of operations. Starbucks Australia segment would scale up its operations again if proper marketing, strategic alliances, proper analysis of the industrial and general environment for the corporation is done Australia. The following proposed solutions based on porters’ competitive forces model would most likely work for Starbucks Australia. Marketing For the case of Starbucks Australia, it is a common fact that Starbucks marketing concept of blanketing a location did not work for the Australian segment showing that some unique Australian marketing is required. The blanketing marketing idea has been the key to market penetration by Starbuck especially in the US market but it is always good to appreciate that different environments require different solutions. For the Australian segment it will be a nice idea if Starbuck will give it a try to the concept of commercial advertising since most of its competitors have been doing the same. Australian awareness of the Starbucks products should be increased through a more effective promotion, advertising and marketing. Marketing through networking and customer experiences will only be supportive for the case of Australian segment unlike the US segment. Starbuck marketing should be as creative as ever, localizing its brand does not necessary mean losing the original brand concept. Even a localized packaging concept should be able to allow them a market penetration opportunity. Strategic Alliances Starbucks has been enteri ng into strategic alliances in other countries. For the case of Australia, it will be much strategic to do the same. There are a lot of local coffee stores and firms which Starbuck can make a joint venture offer or a takeover bid where necessary. This will make the competitors strategic partners of Starbucks. Trading under a locally registered wholly owned subsidiary for Starbuck not only can allow a local attachment and market but it also spreads the business risks for the corporation. With the culture of Australian having more attachments to their own cultures, foods and enterprises coupled with the human tendencies of ‘appreciating their own’, it will be necessary that Starbucks should have any form of strategic alliance with a local firm. Financial Aspects Most of Starbucks stores closed in Australia have not been able to break-even in the business showing that costs management might also have contributed to the loss making scenario. Starbucks Australia should also have a management change so as to align the financial management and cost control with the corporate Strategy of expansion. The financial management aspect will enable Starbucks Australia an opportunity to develop a product mix that will allow the company experience increased sales with a low cost production. Financial management Strategy is always underlying every corporate strategy hence for an efficient and successful project implementation, it necessary to ensure that the company’s financial management strategy and team is in place (Vernon, 2008). This team should have the relevant capacity and experience in the market segment where the project will be implemented. Industry environment This is the environment under which Starbucks Corporation operates globally and even locally in Australia. This environment will constitute; suppliers, competitors, substitute products and new entrants. Porters’ competitive forces model is founded on the view of the firm within its i ndustrial environment. Competitive forces faced by firms include; supplier bargaining power, customer bargaining power, substitute’s threats, and fresh entrants threats (Mellahi, 2000). Starbucks Australia has faces almost all of these competitive forces in their Australian market hence necessary actions are required to counter. With these forces resulting in the downsizing of Starbucks Australia’s Segment, the following remedial actions will be necessary; Bargaining power of suppliers Starbucks supply chain globally is well established and efficient. Failure to for a corporation like Starbuck to maintain on its quality standards and fair pricing of its coffee will allow competitors an upper hand in the market. Starbucks Australia should consider an option for local suppliers so as to reduce on their costs of importing from the US. It will be much cheaper if Starbucks can be strategic and negotiate with a local coffee supplier for branding in Australia. It should also used technology to build a value chain relationship with local suppliers. This will give an upper hand in the competition and can even play a role as a major distributor other than retailing after all its major objective is profitability. With the global presence of Starbuck, building proper linkages with supplier can in fact give them strategic advantage in the coffee business. Since the retail business has faced enough challenges, Starbuck should give it a try to compete at the distribution line, a higher level competition. Bargaining power of customers Customers are very critical for the success of any corporate business. They are the greatest test of products quality. With no grouping of customers to fight for their interest, they will only express themselves in terms of low and high demand (Slack, 2009). If the customers demand for a product is high it indicates high quality and a very fair price. For the low demand of Starbucks products the pricing and preferences qualities ha ve been the most contributing factors. Starbucks should therefore head the customers’ feedback and try to meet their needs hence they got no business being in the market. Substitutes and other products Substitute products in the Starbucks Australia segment posed a major threat to the Starbucks brand in Australia. Even though known to be an international brand with high quality, Starbucks products couldn’t compete effectively to beat Gloria and Melbourne coffee brand. It is now necessary that Starbucks if it still requires regaining the Australian market should engage in an innovative product differentiation exercise. It should be able to penetrate the market with wide ranging products in varying prices. This product mix should be able to cover the whole market clusters from the low income to the high end market. Substitutes of Starbucks products mainly tea and cocoa are not their main threat but their impact should only be checked through rigorous marketing and promoti ons. Competitors’ actions With the entrance of Starbucks in to the Australian market, its competitors definitely didn’t like it. The competition for customers has gone up and to some extend Starbucks is giving in some market share to its competitors. Starbucks has faced a serious price challenge where it has been perceived as dealing with overpriced products. Though this branding is relevant to the high end market usually other potential customers would be denied a chance to be part of the clientele. Starbucks should be able to practice price and product differentiation or develop innovative products to fit to the low end market. It is necessary that Starbucks should develop products that are low cost that are able to compete effectively in the local market. These products should have an image of being locally processed products and it should actually have an Australian concept in its processing. With the local sourcing of inputs and low cost local concept products by a local brand or firm, I do believe that Starbucks will successfully beat competition in Australia and definitely achieve its global expansion strategy With the firm grip on the worldwide industry, Starbucks should be able to be much profitable and competitors will not benefit from the economies of scale. The Gloria jean coffee, Espresso and local Melbourne coffee will be local and small scale but they are taking a share of the coffee market in Australia consequently Starbucks should be careful of their actions. Starbucks policy on great customer experience should be used in this market so as to retain customers. New entrants The coffee industry is very competitive and lucrative therefore new investors into the industry are bound to get in. Starbucks Australia needs to be maintaining their market share and profitability. In order for this threat to be countered, Starbucks should therefore maintain high level customer retention and high quality products. General Environment This is a n environment which is outside the industry. This will include the Political, population, social, global and economic environment. Starbuck Australia is affected by the Australian government corporate tax rates and other regulations but the major challenge of the institution has not been political. Starbucks Australia should take advantage of the high percentage of the young population since most coffee consumers are the youth. The demographic spread initially did not favor the initial locations of the Starbucks stores therefore various stores had to be closed due to low population in their customer catchment area. Population spread therefore is a necessary consideration in the location establishment of the Australian Starbucks stores. The social tie between the Starbucks products and the local community is a necessary. This is because the Australians perception of Starbucks as a foreign coffee brand should be curtailed so as to improve on their demand. The economic environment is o ne challenge that usually poses threat to demand of industrial products but for our case this challenge is not the cause of Starbucks Australia’s problems. Conclusion Starbucks Corporation Australia has downsized because of a wrong market penetration strategy coupled with operational inefficiencies. With a clear global corporate strategy of being the market leader, store level operational efficiency and great customer experience which could not work for Starbucks Australia. This calls for a more localized operational strategy which will include effective marketing and promotion plans, proper financial management strategy, product differentiation and necessary supply chain management. Global strategy needs leverage on cutting edge technology, compliance to the regulatory authorities and employee welfare among other issues so as to have successful execution. Starbucks Australia can turn around and this turn around need not be based on blanketing marketing strategy but a relevan t Australian segment operational strategy. References Choo, W., Bontis, N., 2002. The Strategic Management of Intellectual Capital And Organizational Knowledge. 1st ed. London: Oxford University Press. Harley, W., 2004. Global strategic management. 1st ed. Texas: Wiley. Mellahi, K., 2000. Strategic management: an introduction to business and corporate strategy. 2nd ed. New York: Pearson Education. Slack, N., 2009. Operations and process management: principles and practice for strategic impact. 2nd ed. California: Prentice Hall. Vernon, H., 2008. Global strategic management: the essentials. 2nd ed. Texas: Wiley. This research paper on The Application of Global Strategic Management model to Problems that Starbucks faces in Australia was written and submitted by user Haiden Y. to help you with your own studies. You are free to use it for research and reference purposes in order to write your own paper; however, you must cite it accordingly. You can donate your paper here.

Architect William Holabird and the First Skyscrapers

Architect William Holabird and the First Skyscrapers Architect William Holabird (born September 11, 1854 in Amenia Union, New York), along with his partner Martin Roche (1853-1927), forged Americas early skyscrapers and launched an architectural style known as the Chicago School. The architectural firms of Holabird and Roche, Burnham and Root, and Adler and Sullivan were some of the most influential teams in American architectural history and modern design. William Holabird began his education at the West Point Military Academy, but after two years he moved to Chicago and worked as a draftsman for William Le Baron Jenney, who is often called Father of the Skyscraper. Holabird founded his own practice in 1880, and formed a partnership with Martin Roche in 1881. The Chicago School style featured many innovations. The Chicago window created the effect that the buildings were composed of glass. Each large pane of glass was flanked by narrow windows that could be opened. Many of the first skyscrapers were built in Chicago, Illinois after the Great Fire of 1871. In Chicago, Holabird and Roche designed the Tacoma Building (1888), the Pontiac Building (1891), the Old Colony Building (1893), the Marquette Building (1895), the LaSalle Hotel (1909), the Brooks Building (1910), the Palmer House (1923), and the Stevens Hotel (1927). Between 1889 and 1908 Holabird and Roche built a number of buildings at Fort Sheridan, Illinois - 66 buildings have been designated a National Historic Landmark District. In addition to their Chicago skyscrapers, Holabird and Roche became leading designers of large hotels in the midwest. The Plankinton Building in Milwaukee Wisconsin started off as a two-story building in 1916 and five more floors were added in 1924. The Plankinton, like other new tall buildings being built at the time, was steel frame with a facade of terra cotta.   After William Holabirds death on July 19, 1923, the firm was reorganized by his son. The new firm, Holabird Root, was highly influential in the 1920s. The John D. and Catherine T. MacArthur Foundation is proud to own and occupy the Marquette Building in Chicago. As a supporter of creativity, the Foundation is the perfect owner of a building steeped in history. Early skyscrapers from the Chicago School era are now over a century old, if they havent already been torn down. Holabird and Roche designed the original 1924 neoclassical style Soldier Field in Chicago, a national landmark stripped of its designation after a gut-wrenching 21st century renovation. Restoration and historic preservation are the price of caring for history.

Business case Essay Example | Topics and Well Written Essays - 1750 words

Business case - Essay Example By ensuring that blind people are able to transact with the bank just like the other people, the bank will bridge the gap in between people who are physically impaired and the ones’ that are not. Consequently, it will enable the bank to broaden its customer base and improve its profitability. The purpose of this activity is to act ethically responsible and allow equal opportunities to the physically challenged people (ProTrain). It will help to bring such people into the mainstream of the population in terms of business transactions. Hence, it will be a source of business of the bank. Furthermore, it will help such people to avail the facilities of the bank to their own advantage. Since, there is a strong need in the market to cater to the blind customers the bank has decided to introduce a new system which will ease the process of banking for the blind people. Thus, it will ensure that both the people and the bank have mutual benefits. Previously the bank did not employ any special routines to cater to the blind people. The need was felt to facilitate these people and give them an opportunity to run their own accounts, manage their own funds and monitor their accounts’ progress by personally checking their bank statements and other details. Thus, a need arose for a special procedure that will be able to fulfill the needs of the blind customers. As a result the bank has decided to implement a system whereby all correspondence to the blind customers, i.e. their bank statements, terms and conditions statements, applications etc will be used using Braille. In the current business scenario blind people are not offered a self reliant solution for their banking needs. In order to conduct business they are usually assisted by someone and have to be explained whatever is being given to them. Therefore, without assistance it is impossible for the blind

Grading and Recommendation Assessment Assignment

Grading and Recommendation Assessment - Assignment Example This could be measured through the utilization of trial and error process wherein the practice is tried and tested as to how much it could attest to the needed specifications of a particular need to which the evidence based practice has been basically made for. After the trial and error procedure, the weaknesses and the strengths of the process shall be identified. Likely, the strengths would depend on how the stakeholders responded to the program or the process applied through the use of the evidence-based practice. If the participants responded well with lesser level of error occurrences, then the practice tried and tested could be noted to have a strong implicative effect on the things that it is supposed to have direct changes on. Meanwhile, even though it has been proven strong, it should still be measured and identified with the possible weaknesses it has. Through this, the specification of the needed advancement could still be recognized as part of its possible improvement in the future. If these procedures are specifically carried on, it could be expected that the upcoming GRADE system could be well assured to have a better effect in approving or disapproving evidenced based practices that are used for the specific

User Interfaces Ic Compiler Computer Science Essay

User Interfaces Ic Compiler Computer Science Essay IC Compiler is the software package from Synopsys for Physical Design of ASIC. It provides necessary tools to complete the back end design of the very deep submicron designs. The inputs to the IC Compiler are: a gate-level netlist which can be from DC Compiler or third-party tools, a detailed floorplan which can be from previous Design Planning through IC Compiler or other third-party tools, timing constraints and other constraints, physical and timing libraries provided by manufacturer, and foundry-process data. IC Compiler generates a GDSII-format file as output ready for tape out of the chip. In addition, it is possible to export a Design Exchange Format (DEF) file of placed netlist data ready for a third-party router. IC Compiler uses a binary Synopsys Milkyway database, which can be used by other Synopsys tools based on Milkyway. [16] 4.2 User Interfaces IC Compiler can be used either with Shell interface (icc_shell) or with Graphical user interface (GUI). Shell interface is the command-line interface, which is used for batch mode, scripts, typing commands, and push-button type of operations. Graphical user interface (GUI) is an advanced graphical analysis and physical editing tool. Certain tasks, such as very accurately displaying the design and providing visual analysis tools, can only performed from the GUI. Also tool command language (Tcl), which is used in many applications in the EDA industry, is available to IC Compiler. Using Tcl, you can write reusable procedures and scripts. The IC Compiler design flow is an easy-to-use, single-pass flow that provides convergent timing closure. Figure 4.1 shows the basic IC Compiler design flow, which is centered around three core commands that perform placement and optimization (place_opt), clock tree synthesis and optimization (clock_opt), and routing and postroute optimization (route_opt). [16] icc1 Figure 4.1 IC Compiler Design Flow [21] For most designs, if the place_opt, clock_opt, and route_opt steps are followed, IC Compiler will provide optimal results. You can use IC Compiler to efficiently perform chip-level design planning, placement, clock tree synthesis and routing on designs with moderate timing and congestion challenges. To further improve the quality of results for your design you can use additional commands and switches for placement, clock tree synthesis, and routing steps that IC Compiler provides. IC Compiler design flow involves execution of following steps: 1. Set up and prepare the libraries and the design data. 2. Perform design planning and power planning. -Design planning is to perform necessary steps to create a floorplan, determine the size of the design, create the boundary and core area, create site rows for the placement of standard cells, set up the I/O pads. -Power planning, is to perform necessary steps to create a power plan to meet the power budget and the target leakage current. 3. Perform placement and optimization. IC Compiler placement and optimization uses enhanced placement and synthesis technologies to generate a legalized placement for leaf cells and an optimized design, which addresses and resolves timing closure issues for the provided design. You can supplement this functionality by optimizing for power, recovering area for placement, minimizing congestion, and minimizing timing and design rule violations. To perform placement and optimization, use the place_opt core command (or from GUI choose Placement menu and then Core Placement and Optimization sub-menu). 4. Perform clock tree synthesis and optimization. To perform the clock tree synthesis and optimization phase, use the command clock_opt (or choose Clock > Core Clock Tree Synthesis and Optimization in the GUI). IC Compiler clock tree synthesis and embedded optimization solve complicated clock tree synthesis problems, such as blockage avoidance and the correlation between preroute and postroute data. Clock tree optimization improves both clock skew and clock insertion delay by performing buffer sizing, buffer relocation, gate sizing, gate relocation, level adjustment, reconfiguration, delay insertion, dummy load insertion, and balancing of interclock delays. 5. Perform routing and postroute optimization. To perform routing and postroute optimization, use the route_opt core command (or choose Route > Core Routing and Optimization in the GUI). As part of routing and postroute optimization, IC Compiler performs global routing, detail routing, track assignment, topological optimization, and engineering change order (ECO) routing. For most designs, the default routing and postroute optimization setup produces optimal results. If necessary, you can supplement this functionality by optimizing routing patterns and reducing crosstalk or by customizing the routing and postroute optimization functions for special needs. 6. Perform chip finishing and design for manufacturing tasks. IC Compiler provides chip finishing and design for manufacturing and yield capabilities that you can apply throughout the various stages of the design flow to address process design issues encountered during chip manufacturing. 7. Save the design. Save your design in the Milkyway format. This format is the internal database format used by IC Compiler to store all the logical and physical information about a design. [16] 4.3 How to Invoke the IC Compiler 1. Log in to the UNIX environment with the user id and password . 2. Start IC Compiler from the UNIX promt: UNIX$ icc_shell The xterm unix prompt turns into the IC Compiler shell command prompt. 3. Start the GUI. icc_shell> start_gui This window can display schematics and logical browsers, among other things, once a design is loaded. 4.4 Preparing the Design IC Compiler uses a Milkyway design library to store design and its associated library information. This section describes how to set up the libraries, create a Milkyway design library, read your design, and save the design in Milkyway format. These steps are explained in the following sections: à ¢Ã¢â€š ¬Ã‚ ¢ Setting Up the Libraries à ¢Ã¢â€š ¬Ã‚ ¢ Setting Up the Power and Ground Nets à ¢Ã¢â€š ¬Ã‚ ¢ Reading the Design à ¢Ã¢â€š ¬Ã‚ ¢ Annotating the Physical Data à ¢Ã¢â€š ¬Ã‚ ¢ Preparing for Timing Analysis and RC Calculation à ¢Ã¢â€š ¬Ã‚ ¢ Saving the Design 4.4.1 Setting Up the Libraries IC Compiler requires both logic libraries and physical libraries. The following sections describe how to set up and validate these libraries. à ¢Ã¢â€š ¬Ã‚ ¢ Setting Up the Logic Libraries: IC Compiler uses logic libraries to provide timing and functionality information for all standard cells. In addition, logic libraries can provide timing information for hard macros, such as RAMs. IC Compiler uses variables to define the logic library settings. In each session, you must define the values for the following variables (either interactively, in the .synopsys_dc.setup file, or by restoring the values saved in the Milkyway design library) so that IC Compiler can access the libraries: à ¢Ã¢â€š ¬Ã‚ ¢ search_path Lists the paths where IC Compiler can locate the logic libraries. à ¢Ã¢â€š ¬Ã‚ ¢ target_library Lists the logic libraries that IC Compiler can use to perform physical optimization. à ¢Ã¢â€š ¬Ã‚ ¢ link_library Lists the logic libraries that IC Compiler can search to resolve references. à ¢Ã¢â€š ¬Ã‚ ¢ Setting Up the Physical Libraries: IC Compiler uses Milkyway reference libraries and technology (.tf) files to provide physical library information. The Milkyway reference libraries contain physical information about the standard cells and macro cells in your technology library. In addition, these reference libraries define the placement unit tile. The technology files provide information such as the names and characteristics (physical and electrical) for each metal layer, which are technology-specific. The physical library information is stored in the Milkyway design library. For each cell, the Milkyway design library contains several views of the cell, which are used for different physical design tasks. If you have not already created a Milkyway library for your design (by using another tool that uses Milkyway), you need to create one by using the IC Compiler tool. If you already have a Milkyway design library, you must open it before working on your design. This section describes how to perform the following tasks: à ¢Ã¢â€š ¬Ã‚ ¢ Create a Milkyway design library To create a Milkyway design library, use the create_mw_lib command (or choose File > Create Library in the GUI). à ¢Ã¢â€š ¬Ã‚ ¢ Open a Milkyway design library To open an existing Milkyway design library, use the open_mw_lib command (or choose File > Open Library in the GUI). à ¢Ã¢â€š ¬Ã‚ ¢ Report on a Milkyway design library To report on the reference libraries attached to the design library, use the -mw_reference_library option. icc_shell>report_mw_lib-mw_reference_library design_library_name To report on the units used in the design library, use the report_units command. icc_shell> report_units à ¢Ã¢â€š ¬Ã‚ ¢ Change the physical library information To change the technology file, use the set_mw_technology_file command (or choose File > Set Technology File in the GUI) to specify the new technology file name and the name of the design library. à ¢Ã¢â€š ¬Ã‚ ¢ Save the physical library information To save the technology or reference control information in a file for later use, use the write_mw_lib_files command (or choose File > Export > Write Library File in the GUI). In a single invocation of the command, you can output only one type of file. To output both a technology file and a reference control file, you must run the command twice. à ¢Ã¢â€š ¬Ã‚ ¢ Verifying Library Consistency: Consistency between the logic library and the physical library is critical to achieving good results. Before you process your design, ensure that your libraries are consistent by running the check_library command. [16] icc_shell> check_library 4.4.2 Setting Up the Power and Ground Nets IC Compiler uses variables to define names for the power and ground nets. In each session, you must define the values for the following variables (either interactively or in the .synopsys_dc.setup file) so that IC Compiler can identify the power and ground nets: à ¢Ã¢â€š ¬Ã‚ ¢ mw_logic0_net By default, IC Compiler VSS as the ground net name. If you are using a different name, you must specify the name by setting the mw_logic0_net variable. à ¢Ã¢â€š ¬Ã‚ ¢ mw_logic1_net By default, IC Compiler uses VDD as the power net name. If you are using a different name, you must specify the name by setting the mw_logic1_net variable. 4.4.3 Reading the Design IC Compiler can read designs in either Milkyway or ASCII (Verilog, DEF, and SDC files) format. à ¢Ã¢â€š ¬Ã‚ ¢ Reading a Design in Milkyway Format à ¢Ã¢â€š ¬Ã‚ ¢ Reading a Design in ASCII Format 4.4.4 Annotating the Physical Data IC Compiler provides several methods of annotating physical data on the design: à ¢Ã¢â€š ¬Ã‚ ¢ Reading the physical data from a DEF file To read a DEF file, use the read_def command (or choose File > Import > Read DEF in the GUI). icc_shell> read_def -allow_physical design_name.def à ¢Ã¢â€š ¬Ã‚ ¢ Reading the physical data from a floorplan file A floorplan file is a file that you previously created by using the write_floorplan command (or by choosing Floorplan > Write Floorplan in the GUI). icc_shell> read_floorplan floorplan_file_name à ¢Ã¢â€š ¬Ã‚ ¢ Copying the physical data from another design To copy physical data from the layout (CEL) view of one design in the current Milkyway design library to another, use the copy_floorplan command (or choose Floorplan > Copy Floorplan in the GUI). [16] icc_shell> copy_floorplan -from design1 4.4.5 Preparing for Timing Analysis and RC Calculation IC Compiler provides RC calculation technology and timing analysis capabilities for both preroute and postroute data. Before you perform RC calculation and timing analysis, you must complete the following tasks: à ¢Ã¢â€š ¬Ã‚ ¢ Set up the TLUPlus files You specify these files by using the set_tlu_plus_files command (or by choosing File > Set TLU+ in the GUI). icc_shell> set_tlu_plus_files -tech2itf_map ./path/map_file_name.map -max_tluplus ./path/worst_settings.tlup -min_tluplus ./path/best_settings.tlup à ¢Ã¢â€š ¬Ã‚ ¢ (Optional) Back-annotate delay or parasitic data To back-annotate the design with delay information provided in a Standard Delay Format (SDF) file, use the read_sdf command (or choose File > Import > Read SDF in the GUI). To remove annotated data from design, use the remove_annotations command. à ¢Ã¢â€š ¬Ã‚ ¢ Set the timing constraints At a minimum, the timing constraints must contain a clock definition for each clock signal, as well as input and output arrival times for each I/O port. This requirement ensures that all signal paths are constrained for timing. To read a timing constraints file, use the read_sdc command (or choose File > Import > Read SDC in the GUI). icc_shell> read_sdc -version 1.7 design_name.sdc à ¢Ã¢â€š ¬Ã‚ ¢ Specify the analysis mode Conditions such as fabrication process, operating temperature, and power supply voltage can vary semiconductor device parameters. You can specify the operating conditions for analysis with the set_operating_conditions command. à ¢Ã¢â€š ¬Ã‚ ¢ (Optional) Set the derating factors If your timing library does not include minimum and maximum timing data, you can perform simultaneous minimum and maximum timing analysis by specifying derating factors for your timing library. Use the set_timing_derate command to specify the derating factors. à ¢Ã¢â€š ¬Ã‚ ¢ Select the delay calculation algorithm By default, IC Compiler uses Elmore delay calculation for both preroute and postroute delay calculations. For postroute delay calculations, you can choose to use Arnoldi delay calculation either for clock nets only or for all nets. Elmore delay calculation is faster, but its results do not always correlate with the PrimeTime and PrimeTime SI results. The Arnoldi calculation is best used for designs with smaller geometries and high resistive nets, but it requires more runtime and memory. [16] 4.4.6 Saving the Design To save the design in Milkyway format, use the save_mw_cel command (or choose File > Save Design in the GUI). [16] CHAPTER 5: Design Planning 5.1 Introduction Design planning in IC Compiler provides basic floorplanning and prototyping capabilities such as dirty-netlist handling, automatic die size exploration, performing various operations with black box modules and cells, fast placement of macros and standard cells, packing macros into arrays, creating and shaping plan groups, in-place optimization, prototype global routing analysis, hierarchical clock planning, performing pin assignment on soft macros and plan groups, performing timing budgeting, converting the hierarchy, and refining the pin assignment. Power network synthesis and power network analysis functions, applied during the feasibility phase of design planning, provide automatic synthesis of local power structures within voltage areas. Power network analysis validates the power synthesis results by performing voltage-drop and electromigration analysis. [16] Figure 5.1 IC Compiler Design Planning [21] 5.2 Tasks to be performed during Design Planning à ¢Ã¢â€š ¬Ã‚ ¢ Initializing the Floorplan à ¢Ã¢â€š ¬Ã‚ ¢ Automating Die Size Exploration à ¢Ã¢â€š ¬Ã‚ ¢ Handling Black Boxes à ¢Ã¢â€š ¬Ã‚ ¢ Performing an Initial Virtual Flat Placement à ¢Ã¢â€š ¬Ã‚ ¢ Creating and Shaping Plan Groups à ¢Ã¢â€š ¬Ã‚ ¢ Performing Power Planning à ¢Ã¢â€š ¬Ã‚ ¢ Performing Prototype Global Routing à ¢Ã¢â€š ¬Ã‚ ¢ Performing Hierarchical Clock Planning à ¢Ã¢â€š ¬Ã‚ ¢ Performing In-Place Optimization à ¢Ã¢â€š ¬Ã‚ ¢ Performing Routing-Based Pin Assignment à ¢Ã¢â€š ¬Ã‚ ¢ Performing RC Extraction à ¢Ã¢â€š ¬Ã‚ ¢ Performing Timing Analysis à ¢Ã¢â€š ¬Ã‚ ¢ Performing Timing Budgeting à ¢Ã¢â€š ¬Ã‚ ¢ Committing the Physical Hierarchy à ¢Ã¢â€š ¬Ã‚ ¢ Refining the Pin Assignment 5.3 Initializing the Floorplan The steps in initializing the floorplan are described below. à ¢Ã¢â€š ¬Ã‚ ¢ Reading the I/O Constraints: To load the top-level I/O pad and pin constraints, use the read_io_constraints command. à ¢Ã¢â€š ¬Ã‚ ¢ Defining the Core and Placing the I/O Pads: To define the core and place the I/O pads and pins, use the initialize_floorplan command. à ¢Ã¢â€š ¬Ã‚ ¢ Creating Rectilinear-Shaped Blocks: Use the initialize_rectilinear_block command to create a floorplan for rectilinear blocks from a fixed set of L, T, U, or cross-shaped templates. These templates are used to determine the cell boundary and shape of the core. To do this, use initialize_rectilinear_block -shape L|T|U|X. à ¢Ã¢â€š ¬Ã‚ ¢ Writing I/O Constraint Information: To write top-level I/O pad or pin constraints, use the write_io_constraints command. Read the Synopsys Design Constraints (SDC) file (read_sdc command) to ensure that all signal paths are constrained for timing. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Cell Rows: To add cell rows, use the add_row command. à ¢Ã¢â€š ¬Ã‚ ¢ Removing Cell Rows: To remove cell rows, use the cut_row command. à ¢Ã¢â€š ¬Ã‚ ¢ Saving the Floorplan Information: To save the floorplan information, use the write_floorplan command. à ¢Ã¢â€š ¬Ã‚ ¢Writing Floorplan Physical Constraints for Design Compiler Topographical Technology: IC Compiler can now write out the floorplan physical constraints for Design Compiler Topographical Technology (DC-T) in Tcl format. The reason for using floorplan physical constraints in the Design Compiler topographical technology mode is to accurately represent the placement area and to improve timing correlation with the post-place-and-route design. The command syntax is: write_physical_constraints -output output_file_name -port_side [16] Figure 5.2 Floor Plan After Initialization [21] 5.4 Automating Die Size Exploration This section describes how to use MinChip technology in IC Compiler to automate the processes exploring and identifying the valid die areas to determine smallest routable, die size for your design while maintaining the relative placement of hard macros, I/O cells, and a power structure that meets voltage drop requirements. The technology is integrated into the Design Planning tool through the estimate_fp_area command. The input is a physically flat Milkyway CEL view. 5.5 Handling Black Boxes Black boxes can be represented in the physical design as either soft or hard macros. A black box macro has a fixed height and width. A black box soft macro sized by area and utilization can be shaped to best fit the floorplan. To handle the black boxes run the following set of commands. set_fp_base_gate estimate_fp_black_boxes flatten_fp_black_boxes create_fp_placement place_fp_pins create_qtm_model qtm_bb set_qtm_technology -lib library_name create_qtm_port -type clock $port report_qtm_model write_qtm_model -format qtm_bb report_timing qtm_bb 5.6 Performing an Initial Virtual Flat Placement The initial virtual flat placement is very fast and is optimized for wire length, congestion, and timing. The way to perform an initial virtual flat placement is described below. à ¢Ã¢â€š ¬Ã‚ ¢ Evaluating Initial Hard Macro Placement: No straightforward criteria exist for evaluating the initial hard macro placement. Measuring the quality of results (QoR) of the hard macro placement can be very subjective and often depends on practical design experience. à ¢Ã¢â€š ¬Ã‚ ¢ Specifying Hard Macro Placement Constraints: Different methods can be use to control the preplacement of hard macros and improve the QoR of the hard macro placement. Creating a User-Defined Array of Hard Macros Setting Floorplan Placement Constraints On Macro Cells Placing a Macro Cell Relative to an Anchor Object Using a Virtual Flat Placement Strategy Enhancing the Behavior of Virtual Flat Placement With the macros_on_edge Switch Creating Macro Blockages for Hard Macros Padding the Hard Macros à ¢Ã¢â€š ¬Ã‚ ¢ Padding the Hard Macros: To avoid placing standard cells too close to macros, which can cause congestion or DRC violations, one can set a user-defined padding distance or keepout margin around the macros. One can set this padding distance on a selected macros cell instance master.During virtual flat placement no other cells will be placed within the specified distance from the macros edges. [16] To set a padding distance (keepout margin) on a selected macros cell instance master, use the set_keepout_margin command. à ¢Ã¢â€š ¬Ã‚ ¢ Placing Hard Macros and Standard Cells: To place the hard macros and standard cells simultaneously, use the create_fp_placement command. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Floorplan Editing: IC Compiler performs the following floorplan editing operations. Creating objects Deleting objects Undoing and redoing edit changes Moving objects Changing the way objects snap to a grid Aligning movable objects 5.7 Creating and Shaping Plan Groups This section describes how to create plan groups for logic modules that need to be physically implemented. Plan groups restrict the placement of cells to a specific region of the core area. This section also describes how to automatically place and shape objects in a design core, add padding around plan group boundaries, and prevent signal leakage and maintain signal integrity by adding modular block shielding to plan groups and soft macros. The following steps are covered for Creating and Shaping Plan Groups. à ¢Ã¢â€š ¬Ã‚ ¢ Creating Plan Groups: To create a plan group, create_plan_groups command. To remove (delete) plan groups from the current design, use the remove_plan_groups command. à ¢Ã¢â€š ¬Ã‚ ¢ Automatically Placing and Shaping Objects In a Design Core: Plan groups are automatically shaped, sized, and placed inside the core area based on the distribution of cells resulting from the initial virtual flat placement. Blocks (plan groups, voltage areas, and soft macros) marked fix remain fixed; the other blocks, whether or not they are inside the core, are subject to being moved or reshaped. To automatically place and shape objects in the design core, shape_fp_blocks command. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Padding to Plan Groups: To prevent congestion or DRC violations, one can add padding around plan group boundaries. Plan group padding sets placement blockages on the internal and external edges of the plan group boundary. Internal padding is equivalent to boundary spacing in the core area. External padding is equivalent to macro padding. To add padding to plan groups, create_fp_plan_group_padding command. To remove both external and internal padding for the plan groups, use the remove_fp_plan_group_padding command. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Block Shielding to Plan Groups or Soft Macros: When two signals are routed parallel to each other, signal leakage can occur between the signals, leading to an unreliable design. One can protect signal integrity by adding modular block shielding to plan groups and soft macros. The shielding consists of metal rectangles that are created around the outside of the soft macro boundary in the top level of the design, and around the inside boundary of the soft macro. To add block shielding for plan groups or soft macros, use the create_fp_block_shielding command. To remove the signal shielding created by modular block shielding, use the remove_fp_block_shielding command. [16] 5.8 Performing Power Planning After completed the design planning process and have a complete floorplan, one can perform power planning, as explained below. à ¢Ã¢â€š ¬Ã‚ ¢ Creating Logical Power and Ground Connections: To define power and ground connections, use the connect_pg_nets command. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Power and Ground Rings: It is necessary to add power and ground rings after doing floorplanning. To add power and ground rings, use the create_rectangular_rings command. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Power and Ground Straps: To add power and ground straps, use the create_power_straps command. à ¢Ã¢â€š ¬Ã‚ ¢ Prerouting Standard Cells: To preroute standard cells, use the preroute_standard_cells command. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Low-Power Planning for Multithreshold-CMOS Designs: One can perform floorplanning for low-power designs by employing power gating. Power gating has the potential to reduce overall power consumption substantially because it reduces leakage power as well as switching power. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Power Network Synthesis: As the design process moves toward creating 65-nm transistors, issues related to power and signal integrity, such as power grid generation, voltage (IR) drop, and electromigration, have become more significant and complex. In addition, this complex technology lengthens the turnaround time needed to identify and fix power and signal integrity problems. By performing power network synthesis one can preview an early power plan that reduces the chances of encountering electromigration and voltage drop problems later in the detailed power routing. To perform the PNS, one can run the set of following commands. [16] synthesize_fp_rail set_fp_rail_constraints set_fp_rail_constraints -set_ring set_fp_block_ring_constraints set_fp_power_pad_constraints set_fp_rail_region_constraints set_fp_rail_voltage_area_constraints set_fp_rail_strategy à ¢Ã¢â€š ¬Ã‚ ¢ Committing the Power Plan: Once the IR drop map meets the IR drop constraints, one can run the commit_fp_rail command to transform the IR drop map into a power plan. à ¢Ã¢â€š ¬Ã‚ ¢ Handling TLUPlus Models in Power Network Synthesis: Power network synthesis supports TLUPlus models. set_fp_rail_strategy -use_tluplus true à ¢Ã¢â€š ¬Ã‚ ¢ Checking Power Network Synthesis Integrity: Initially, when power network synthesis first proposes a power mesh structure, it assumes that the power pins of the mesh are connected to the hard macros and standard cells in the design. It then displays a voltage drop map that one can view to determine if it meets the voltage (IR) drop constraints. After the power mesh is committed, one might discover problem areas in design as a result of automatic or manual cell placement. These areas are referred to as chimney areas and pin connect areas. To Check the PNS Integrity one can run the following set of commands. set_fp_rail_strategy -pns_commit_check_file set_fp_rail_strategy -pns_check_chimney_file set_fp_rail_strategy -pns_check_chimney_file pns_chimney_report set_fp_rail_strategy -pns_check_hor_chimney_layers set_fp_rail_strategy -pns_check_chimney_min_dist set_fp_rail_strategy -pns_check_pad_connection file_name set_fp_rail_strategy -pns_report_pad_connection_limit set_fp_rail_strategy -pns_report_min_pin_width set_fp_rail_strategy -pns_check_hard_macro_connection file_name set_fp_rail_strategy -pns_check_hard_macro_connection_limit set_fp_rail_strategy -pns_report_min_pin_width à ¢Ã¢â€š ¬Ã‚ ¢ Analyzing the Power Network: One perform power network analysis to predict IR drop at different floorplan stages on both complete and incomplete power nets in the design. To perform power network analysis, use the analyze_fp_rail command. To add virtual pads, use the create_fp_virtual_pad command. To ignore the hard macro blockages, use the set_fp_power_plan_constraints command. à ¢Ã¢â€š ¬Ã‚ ¢ Viewing the Analysis Results: When power and rail analysis are complete, one can check for the voltage drop and electromigration violations in the design by using the voltage drop map and the electromigration map. One can save the results of voltage drop and electromigration current density values to the database by saving the CEL view that has just been analyzed. à ¢Ã¢â€š ¬Ã‚ ¢ Reporting Settings for Power Network Synthesis and Power Network Analysis Strategies: To get a report of the current values of the strategies used by power network synthesis and power network analysis by using the report_fp_rail_strategy command. [16] 5.9 Performing Prototype Global Routing One can perform prototype global routing to get an estimate of the routability and congestion of the design. Global routing is done to detect possible congestion hot spots that might exist in the floorplan due to the placement of the hard macros or inadequate channel spacing. To perform global routing, use the route_fp_proto command. 5.10 Performing Hierarchical Clock Planning This section describes how to reduce timing closure iterations by performing hierarchical clock planning on a top-level design during the early stages of the virtual flat flow, after plan groups are created and before the hierarchy is committed. One can perform clock planning on a specified clock net or on all clock nets in the design. à ¢Ã¢â€š ¬Ã‚ ¢ Setting Clock Planning Options: To set clock planning options, use the set_fp_clock_plan_options command. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Clock Planning Operations: To perform clock planning operations, use the compile_fp_clock_plan command. à ¢Ã¢â€š ¬Ã‚ ¢ Generating Clock Tree Reports: To generate clock tree reports, use the report_clock_tree command. à ¢Ã¢â€š ¬Ã‚ ¢ Using Multivoltage Designs in Clock Planning: Clock planning supports multivoltage designs. Designs in multivoltage domains operate at various voltages. Multivoltage domains are connected through level-shifter cells. A level-shifter cell is a special cell that can carry signals across different voltage areas. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Plan Group-Aware Clock Tree Synthesis in Clock Planning: With this feature, clock tree synthesis can generate a clock tree that honors the plan groups while inserting buffers in the tree and prevent new clock buffers from being placed on top of a plan group unless they drive the entire subtree inside that particular plan group. This results in a minimum of clock feedthroughs, which makes the design easier to manage during partitioning and budgeting. [16] 5.11 Performing In-Place Optimization In-place optimization is an iterative process that is based on virtual routing. Three types of optimizations are performed: timing improvement, area recovery, and fixing DRC violations. These optimizations prese